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The Eclipse Foundation's IP Team's (currently) experimental repository to explore modernizing the workflow for vetting intellectual property content on behalf of Eclipse project teams.
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This repository is used to track issues involving the EMO, including matters pertaining to the implementation of the Eclipse Foundation Development Process (EDP), Eclipse Foundation Specification Process (EFSP), and Eclipse IP Policy.
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Comma project
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The Eclipse sim@openPASS platform mainly consists of a GUI and a simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/technology.simopenpass
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Gitlab instance running at https://gitlab.eclipse.org/
Quickstart guide for Bugzilla users: https://wiki.eclipse.org/Gitlab
File an issue about the Eclipse GitLab instance here: https://gitlab.eclipse.org/eclipsefdn/gitlab/-/issues
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The Eclipse® IDE Working Group is formed to ensure the continued sustainability, integrity, evolution, and adoption of the Eclipse IDE suite of products and related technologies.
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This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)
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Main Repo for the OpenHW Group Software Task Group
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4 stage, in-order, compute RISC-V core based on the CV32E40P
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4 stage, in-order, secure RISC-V core based on the CV32E40P
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CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
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Documentation for the OpenHW Group's set of CORE-V RISC-V cores
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Functional verification project for the CORE-V family of RISC-V cores.
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OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.
