GitLab

Community support from Eclipse Foundation: IT, Marketing, Legal, etc

Small and simple APB interrupt controller

Unofficial development fork of U-Boot

Linux kernel source tree

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

4 stage, in-order, compute RISC-V core based on the CV32E40P

Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

CVA6 SDK containing RISC-V tools and Buildroot