GitLab

Functional verification project for the CORE-V family of RISC-V cores.

4 stage, in-order, compute RISC-V core based on the CV32E40P

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

4 stage, in-order, secure RISC-V core based on the CV32E40P

OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Main Repo for the OpenHW Group Software Task Group

Instruction Set Generator initially contributed by Futurewei

CVA6 SDK containing RISC-V tools and Buildroot

The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

Eclipse/FreeRTOS/core-v-mcu example program

Unofficial development fork of U-Boot

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.