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OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.

4 stage, in-order, secure RISC-V core based on the CV32E40P

Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)

Small and simple APB interrupt controller

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

Instruction Set Generator initially contributed by Futurewei

4 stage, in-order, compute RISC-V core based on the CV32E40P

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

This is a private repo with tools and 'how-to' documentation for OpenHW Staff to use. We may make this repo public at some point.