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RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

4 stage, in-order, compute RISC-V core based on the CV32E40P

Linux kernel source tree

Small and simple APB interrupt controller

Repository for AWS Infrastructure (Docker, Documentation, etc.)

downloads.openhwgroup.org

Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)