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Community support from Eclipse Foundation: IT, Marketing, Legal, etc

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

Repository for AWS Infrastructure (Docker, Documentation, etc.)

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Main Repo for the OpenHW Group Software Task Group

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

Small and simple APB interrupt controller

Instruction Set Generator initially contributed by Futurewei

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Linux kernel source tree

4 stage, in-order, secure RISC-V core based on the CV32E40P