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Community support from Eclipse Foundation: IT, Marketing, Legal, etc
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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Documentation for the OpenHW Group's set of CORE-V RISC-V cores
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Repository for AWS Infrastructure (Docker, Documentation, etc.)
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Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
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Main Repo for the OpenHW Group Software Task Group
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This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
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RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
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Small and simple APB interrupt controller
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Instruction Set Generator initially contributed by Futurewei
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CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
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Linux kernel source tree
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4 stage, in-order, secure RISC-V core based on the CV32E40P