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RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

Eclipse/FreeRTOS/core-v-mcu example program

Instruction Set Generator initially contributed by Futurewei

Aidge's CUDA backend, written in C++/CUDA and using NVidia's CuDNN and CuBLAS libraries. Required for training and inference on NVidia's GPUs

Aidge's quantization module, for both PTQ and QAT, written in C++

Aidge's C++ export module optimized for ARM Cortex-M

Aidge's learning module, written in C++, required for models training directly in Aidge

A standalone simulator which can be used to run an OpenScenario based simulation.

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

Aidge's core module, written in C++, always required

Aidge's reference CPU backend, written in C++, not optimized for performances

Aidge's reference C++ export module, required for generating standalone C++ static compute graph