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Yocto layer for CVA6

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.

Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board

CVA6 SDK containing RISC-V tools and Buildroot

Instruction Set Generator initially contributed by Futurewei

Changelog POC is a lightweight proof of concept designed to explore and validate the implementation of an automated changelog generation system

Aidge's CUDA backend, written in C++/CUDA and using NVidia's CuDNN and CuBLAS libraries. Required for training and inference on NVidia's GPUs

Policy service exposes policy evaluation endpoints via HTTP API.

Aidge's quantization module, for both PTQ and QAT, written in C++

Aidge meta-repository, which includes the main modules of the Aidge framework as Git submodules, plus the documentation and tutorials.

The site provides date, time and place for the various events (conferences, demo camps, special days, hackathons and trainings) for the Eclipse ecosystem, displayed on a convenient map of the world.

Aidge's learning module, written in C++, required for models training directly in Aidge