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OpenHW Group / backup-20240505 / cvfpu
Apache License 2.0Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
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OpenHW Group / backup-20240505 / cva5
Apache License 2.0The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
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OpenHW Group / backup-20240505 / cv32e41p
Apache License 2.04 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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Eclipse Projects / aidge / aidge_interop_torch
Eclipse Public License 2.0Updated -
Eclipse Projects / aidge / aidge_backend_cpu
Eclipse Public License 2.0Aidge's reference CPU backend, written in C++, not optimized for performances
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Functional verification project for the CORE-V family of RISC-V cores.
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Eclipse Projects / Eclipse Graphene / tutorials
Apache License 2.0Tutorials and container specification
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Eclipse Projects / xfsc / Dev Ops / Testing / BDD Executor
Apache License 2.0Updated -
Mark Pecze / BDD Executor
Apache License 2.0Updated -
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Eclipse Projects / aidge / aidge_backend_cuda
Eclipse Public License 2.0Aidge's CUDA backend, written in C++/CUDA and using NVidia's CuDNN and CuBLAS libraries. Required for training and inference on NVidia's GPUs
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Mark Pecze / Integration Tests_mark
Apache License 2.0Updated -
Eclipse Projects / Eclipse openpass / openscenario1-engine
Eclipse Public License 2.0Updated -
Paul Romahn / opSimulation
Eclipse Public License 2.0The subproject opSimulation mainly consists of the simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/automotive.openpass
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