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Eclipse Projects / Eclipse openpass / opSimulation
Eclipse Public License 2.0The subproject opSimulation mainly consists of the simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/automotive.openpass
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Eclipse Projects / Eclipse openpass / openscenario1-engine
Eclipse Public License 2.0Updated -
Eclipse Projects / aidge / aidge
Eclipse Public License 2.0Aidge meta-repository, which includes the main modules of the Aidge framework as Git submodules, plus the documentation and tutorials.
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Eclipse Projects / xfsc / Federated Catalogue / FC Service
Apache License 2.0Updated -
Eclipse Projects / Eclipse Graphene / eclipse-graphene
Apache License 2.0Graphene installation and maintenance scripts
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Eclipse Projects / aidge / aidge_core
Eclipse Public License 2.0Aidge's core module, written in C++, always required
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Eclipse Projects / aidge / aidge_export_cpp
Eclipse Public License 2.0Aidge's reference C++ export module, required for generating standalone C++ static compute graph
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Eclipse Projects / aidge / aidge_backend_cuda
Eclipse Public License 2.0Aidge's CUDA backend, written in C++/CUDA and using NVidia's CuDNN and CuBLAS libraries. Required for training and inference on NVidia's GPUs
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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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Eclipse Projects / aidge / aidge_backend_cpu
Eclipse Public License 2.0Aidge's reference CPU backend, written in C++, not optimized for performances
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Functional verification project for the CORE-V family of RISC-V cores.
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Eclipse Projects / aidge / aidge_export_tensorrt
Eclipse Public License 2.0Aidge's TensorRT export module. It act as a thin wrapper around NVidia's tools with easy custom operator insertion
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Eclipse Projects / aidge / aidge_export_arm_cortexm
Eclipse Public License 2.0Updated -
Functional verification project for the CORE-V family of RISC-V cores.
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OpenHW Group / backup-20240421 / force-riscv
Apache License 2.0Instruction Set Generator initially contributed by Futurewei
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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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OpenHW Group / backup-20240421 / cv32e40p
Apache License 2.0CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
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