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StatET (Main Repo)

Website documentation for the Eclipse Foundation chat service

GItlab CI job and pipeline templates for Eclipse projects

CVA6 SDK containing RISC-V tools and Buildroot

Yocto layer for CVA6

Instruction Set Generator initially contributed by Futurewei

Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board

Aidge meta-repository, which includes the main modules of the Aidge framework as Git submodules, plus the documentation and tutorials.

Trace4cps project

Aidge's pruning module, written in C++