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CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Functional verification project for the CORE-V family of RISC-V cores.

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The purpose of the repo is to support CORE-V Wally architectural verification

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Read-only wrapper library for OSI (ASAM Open Simulation Interface) to provide easy access to data even in aggregated form

Functional verification project for the CORE-V family of RISC-V cores.

Aidge's TensorRT export module. It act as a thin wrapper around NVidia's tools with easy custom operator insertion

The subproject opSimulation mainly consists of the simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/automotive.openpass