Halting CSR writes in WB
Created by: silabs-oysteink
CSR instructions were not affected by halt_wb. This could lead to CSR writes not being killed at debug entry. Fixes issues #197 (closed) and #198 (closed).
Not SEC clean.
If no external debug is assumed, this change is SEC clean.
WB is halted for two scenarios:
- Debug entry (external, trigger, ebreak). All stages are halted for one cycle before we kill all stages and enter debug.
- While in sleep mode. In this case, there is no instruction in WB, since we insert a bubble after each WFI instruction to guarantee an interruptible bubble in WB
Signed-off-by: Oystein Knauserud Oystein.Knauserud@silabs.com