core updates mscratch when debug request interrupts an illegal CSR instruction

Created by: strichmo

Component

Component:RTL

Steps to Reproduce

Please provide:

1. Use this fork: https://github.com/strichmo/core-v-verif.git strichmo/temp/issue_197
2. 2d1908351bc9df5ee0020e91bb5074c032f529bc
3. makeuvmt comp_corev-dv gen_corev-dv test TEST=corev_rand_debug_ebreak SEED=-668398650
4. Xcelium 21.07.a001 was used to reproduce

After instruction 0x168a an external debug request is entered. Note this instruction is an illegal CSR access.

    168a:	39f07673          	csrrci	x12,0x39f,0
                  csrrc      tp, 0x35f, s8

When the debug handler is entered, the RTL (and RVFI) report that mscratch is updated to 0xf564, but the RVVI claims mscratch should still be 0x18204

238053.000 ns: Illegal instruction (core 0) at PC 0x0000168a:
UVM_ERROR @ 238128.300 ns : uvme_cv32e40x_core_sb.sv(370) uvm_test_top.env.core_sb [CORESB] CSR Mismatch, order: 10235, csr: mscratch, rvfi = 0x0000f564, rvvi = 0x00018204
UVM_ERROR @ 238161.300 ns : uvme_cv32e40x_core_sb.sv(370) uvm_test_top.env.core_sb [CORESB] CSR Mismatch, order: 10236, csr: mscratch, rvfi = 0x0000f564, rvvi = 0x00018204
UVM_ERROR @ 238179.300 ns : uvme_cv32e40x_core_sb.sv(370) uvm_test_top.env.core_sb [CORESB] CSR Mismatch, order: 10237, csr: mscratch, rvfi = 0x0000f564, rvvi = 0x00018204
UVM_ERROR @ 238197.300 ns : uvme_cv32e40x_core_sb.sv(370) uvm_test_top.env.core_sb [CORESB] CSR Mismatch, order: 10238, csr: mscratch, rvfi = 0x0000f564, rvvi = 0x00018204