RVFI misreports MEPC due to csrrw when debug mode is externally requested

Created by: strichmo

Component

Component:RTL

Steps to Reproduce

Please provide:

Use this fork: https://github.com/strichmo/core-v-verif.git branch strichmo/temp/issue_197
2d1908351bc9df5ee0020e91bb5074c032f529bc
makeuvmt comp_corev-dv gen_corev-dv test TEST=corev_rand_debug_ebreak SEED=1092908718
Xcelium 21.07.a001 was used to reproduce

The instruction at 0x12x is a write to MEPC:

     128:	022d0d13          	addi	x26,x26,34 # 146 <init>
                  csrw mepc, x26
     12c:	341d1073          	csrrw	x0,mepc,x26

The RVFI is showing that debug mode is entered after 0x128, but MEPC is reported as showing the updated value from x26 (0x146).

UVM_ERROR @ 456.300 ns : uvme_cv32e40x_core_sb.sv(370) uvm_test_top.env.core_sb [CORESB] CSR Mismatch, order: 13, csr: mepc, rvfi = 0x00000146, rvvi = 0x00000000

Note that it might be that the 0x12c instruction did indeed execute but it was missed on RVFI.