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Eclipse/FreeRTOS/core-v-mcu example program

Instruction Set Generator initially contributed by Futurewei

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

Aidge's core module, written in C++, always required

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

Aidge's core module, written in C++, always required

Aidge's reference CPU backend, written in C++, not optimized for performances

Aidge's core module, written in C++, always required

Module template for creating a new Aidge module

Aidge's reference CPU backend, written in C++, not optimized for performances

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.