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Eclipse Projects / xfsc / TRAIN / Trusted Content Resolver
Apache License 2.0Updated -
Eclipse Projects / Eclipse Graphene / playground-deployer
Apache License 2.0Deploy ai-pipelines with one click to the ai-playground
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Houssem ROUIS / aidge_backend_cpu
Eclipse Public License 2.0Updated -
Houssem ROUIS / aidge_core
Eclipse Public License 2.0Updated -
Eclipse Projects / aidge / aidge
Eclipse Public License 2.0Updated -
Eclipse Projects / xfsc / Federated Catalogue / FC Service
Apache License 2.0Updated -
Eclipse Projects / xfsc / TRAIN / BDD
Apache License 2.0Updated -
Eclipse Projects / aidge / aidge_backend_cuda
Eclipse Public License 2.0Updated -
Eclipse Projects / aidge / aidge_core
Eclipse Public License 2.0Updated -
Eclipse Projects / xfsc / TRAIN / DNS Zone Manager
Apache License 2.0Updated -
Eclipse Projects / aidge / aidge_backend_cpu
Eclipse Public License 2.0Updated -
Functional verification project for the CORE-V family of RISC-V cores.
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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
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OpenHW Group / backup-20231203 / cvfpu
Apache License 2.0Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
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OpenHW Group / backup-20231203 / cv32e40p
Apache License 2.0CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
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OpenHW Group / backup-20231203 / force-riscv
Apache License 2.0Instruction Set Generator initially contributed by Futurewei
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OpenHW Group / backup-20231203 / cve2
Apache License 2.0The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
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