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Instruction Set Generator initially contributed by Futurewei

Main Repo for the OpenHW Group Software Task Group

CORE-V Family of RISC-V Cores

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

Functional verification project for the CORE-V family of RISC-V cores.

Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board

The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.

OpenHW Group is a global, not-for-profit organization where hardware and software designers collaborate on open-source cores, IP, tools, and software. It provides infrastructure to host high-quality open-source hardware projects aligned with industry best practices.

CVA6 SDK containing RISC-V tools and Buildroot

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

Jenkins Pipeline library used internally at the Eclipse Foundation

openMDM is a kit of components and concepts, which can be used to compose applications for measured data management systems. The development of components and concepts is driven by the openMDM Eclipse Working Group. All components and concepts are published under the Eclipse Public License.

See: https://openmdm.org

Library for loading and providing data from an OpenDRIVE map