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CVA6 SDK containing RISC-V tools and Buildroot

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

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The website for the OSPO Alliance, see https://ospo-alliance.org

The Target Management project creates data models and frameworks to configure and manage remote systems (from mainframe to embedded), their connections, and their services.

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.