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CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Functional verification project for the CORE-V family of RISC-V cores.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

The purpose of the repo is to support CORE-V Wally architectural verification

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

Titan Project

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

The subproject opSimulation mainly consists of the simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/automotive.openpass

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

Eclipse ESCET project main repository.