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Eclipse ESCET project main repository.

eTrice

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

Functional verification project for the CORE-V family of RISC-V cores.

The purpose of the repo is to support CORE-V Wally architectural verification

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Functional verification project for the CORE-V family of RISC-V cores.

The purpose of the repo is to support CORE-V Wally architectural verification

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.