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Eclipse ESCET project main repository.

The subproject opSimulation mainly consists of the simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/automotive.openpass

Eclipse ESCET project main repository.

Julian Skublics etrice fork

Aidge meta-repository, which includes the main modules of the Aidge framework as Git submodules, plus the documentation and tutorials.

The Eclipse sim@openPASS platform mainly consists of a GUI and a simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/technology.simopenpass

The OpenPiton Platform

Functional verification project for the CORE-V family of RISC-V cores.

The purpose of the repo is to support CORE-V Wally architectural verification

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Aidge meta-repository, which includes the main modules of the Aidge framework as Git submodules, plus the documentation and tutorials.

CVA6 SDK containing RISC-V tools and Buildroot

Linux kernel source tree

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

CV32E40X Design-Verification environment