Skip to content

GitLab

Explore

Sign in

C

cvw

Project information

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

10,331 Commits
22 Branches
2 Tags
1 Release

README
LICENSE
CONTRIBUTING

Created on

November 20, 2024

Copy SSH clone URLgit@gitlab.eclipse.org:openhw-group/backup-20241120/cvw.git
Copy HTTPS clone URLhttps://gitlab.eclipse.org/openhw-group/backup-20241120/cvw.git

Loading

Copyright © Eclipse Foundation, Inc. All Rights Reserved. Privacy Policy | Terms of Use | Copyright Agent