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The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

The purpose of the repo is to support CORE-V Wally architectural verification

CV32E40X Design-Verification environment

Instruction Set Generator initially contributed by Futurewei

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.

3rd party: Fork of https://github.com/clio-project/meta-binaryaudit

3rd party: Fork of http://git.yoctoproject.org/cgit/cgit.cgi/meta-zephyr/

Oniro Project Documentation

https://gitlab.eclipse.org/eclipse/oniro-blueprints/vending-machine/meta-oniro-blueprints-vending-machine/-/issues/3

Aidge's CUDA backend, written in C++/CUDA and using NVidia's CuDNN and CuBLAS libraries. Required for training and inference on NVidia's GPUs

Example SDK applications for DevKit

Aidge's reference CPU backend, written in C++, not optimized for performances

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

Aidge's CUDA backend, written in C++/CUDA and using NVidia's CuDNN and CuBLAS libraries. Required for training and inference on NVidia's GPUs

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.