Release 4.1.0

Created by: zarubaf

4.1.0

Added

• Official support for floating point unit
• Added AXI-64bit adapter for write-through cache system
• Added AXI atomic ops and exclusive access support to write-through cache system
• Provision riscv-isa-sim tandem simulation
• Support for preloading

Changed

• Rerouted the JTAG from PMOD to second channel of FTDI 2232 chip on Genesys 2 board
• Increase available RAM size on Genesys II board to 1 GiB
• Fixed problem which decoded compressed hints as illegal instructions
• Reduce clock frequency of FPGA to 30 MHz to accomodate FPU
• Bugfixes in write-through cache system
• ID width fix in random delayer