Is it safe to disable and enable data cache at runtime

Created by: jimmysitu

Hi, All

I am trying to work Ariane SoC with a SD controller, which has a DMA engine in it. The cache I use is write-through cache. I need to flush the D cache before DMA move SD blocks to DRAM. As I found in #355 (closed) #339 (closed), the fence instruction do not really flush the write-through cache but only the write buffer. I think a better way is to disable the whole cache and re-enable it. I try it on my FPGA with

    __asm__ volatile("csrwi 0x701, 0x00");
    __asm__ volatile("csrwi 0x701, 0x01");

It seems work, but I am not sure if there is any potential risk. Any comment?

Thanks