L2: Move be (i.e. wstrb for AXI) into the data FIFO (Fixes #6)

Created by: flmeisel

Moved the be signal to the same FIFO as write data. Adapted the L2 interface and its users accordingly.

Tested with a custom design simulation to verify that the issue is fixed, and ran taiga-project's run-compliance-tests-verilator.

Untested: examples/litex/l1_to_wishbone.sv

test_benches/verilator/AXI_DDR_simulation/axi_l2_test.cc is not functional due to compile errors unrelated to these changes.

Fixes #6 (closed)