Cached memory interface: AXI wstrb not stable if AW handshake completes first

Created by: flmeisel

CVA5's dcache memory interface (via l1_arbiter, l2_arbiter, axi_to_arb) starts each single beat AXI AW handshake simultaneously to the only W handshake. The byte enable value be (used for wstrb) is stored alongside the address in the l2_request_t structure, and the FIFO entry is popped as soon as the AW handshake is complete. However, wstrb is in the W handshake alongside wdata.

Scenario: Downstream bus component sets wready only after having accepted an AW handshake. CVA5 will pop from the request FIFO, and wstrb will change to whatever is in the next valid or invalid FIFO element, even though the W handshake is still active.

Effect: Depends on the bus components. In our case (using only Xilinx IP downstream), the presence or absence of an AXI crossbar appears to determine whether wstrb is sampled in the first W handshake cycle, where the AW handshake is still valid and the fault would be hidden, or in a later cycle. In that case, bytes may unintenionally be masked on or off, so data in memory could become inconsistent.

(Suggested) solution: Move be/wstrb to the same FIFO as the write data. I'm preparing a pull request but still doing some validation of the patches for upstream.