(Partial) fix for issue #325.
Created by: silabs-oysteink
Halting EX stage if a CSR write in WB may enable interrupts and at the same time there is an LSU instruction in EX. Fix implemented for both CLIC and basic interrupt mode.
Issue can still occur when X_EXT=1. Fixing this would also need several other fixes for the X-interface.
Signed-off-by: Oystein Knauserud Oystein.Knauserud@silabs.com