[XIF] Too many instructions can execute after interrupt becomes pending and enabled

Created by: Silabs-ArjanB

Version 1.12 of the Privileged Spec states:

After execution of each instruction in program order, if the conditions for an interrupt trap are true, the trap occurs immediately, before another instruction executes.

The CV32E40X (and CV32E40S) break this requirement in case mip is already set and an interrupt should be taken due to enabling it via a CSR write (mip, mie, mstatus, and mideleg) or xRET.

This should become part of the VPLAN as well and should be checked with formal techniques.

Possible fixes include:

• Stall for specific CSR write - load/store/X itf combinations (xRET is likely not an issue thanks to its pipe flush)
• Forwarding of relevant CSR bits into the interrupt logic