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[RISCV] CodeGen Support for XCVsimd Intrinsics

Eclipse Webmaster requested to merge github/fork/realqhc/simd-codegen into development

Created by: realqhc

Code generation from simple add <4 x i8> %a, %b is working right now, however it seems that RVV extension supports VP operations. I am working on bringing support for VP operations to XCVsimd.

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