verilator: Add example TB

Created by: zarubaf

This PR offers preliminary support for a Verilator top-level by adding the necessary fusesoc support. There are a couple of problems with the RTL which will prevent successful execution:

1. The core_v_mcu offers an array of io of which one is the clock and the reset. I have yet to find (or find out if it is possible in general) how to index this in the C++ testbench. For clk, rst, and jtag I think it will be better if we expose them directly. Those ports will always be present. Opinion @timsaxe?
2. When running the simulation verilator complains because of the missing boot data. @gmartin102 where do you currently have the boot data? I assume you do not use the boot_code directory?
3. The pad_frame is stubbed for Verilator. We already discussed that we want to remove the padframe (#113 (closed)).

Signed-off-by: florian@openhwgroup.org