Pads and pad frame

Created by: zarubaf

When bringing up verilator I ran into two issues:

• https://github.com/openhwgroup/core-v-mcu/blob/57c8dc34f3ecbb079cf14c8562b01d73fd9f476d/rtl/core-v-mcu/top/pad_frame.sv#L130 jtag_tdo_i is connected to an output, I guess that is probably a problem with the IO script. @timsaxe
• https://github.com/openhwgroup/core-v-mcu/blob/57c8dc34f3ecbb079cf14c8562b01d73fd9f476d/rtl/vendor/pulp_platform_tech_cells_generic/src/deprecated/pad_functional.sv The pmos and nmos primitives are not supported in Verilator. I would like to have your opinion on whether we can generate the pad frame (including the pads) in a new layer around core_v_mcu (one for the chip and one for the FPGA). That would help us entangle the situation a bit and allow for Verilator simulation.

I'd like to have your input @timsaxe, @gmartin102, @davideschiavone