GitLab

The Eclipse sim@openPASS platform mainly consists of a GUI and a simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/technology.simopenpass

Community support from Eclipse Foundation: IT, Marketing, Legal, etc

Linux kernel source tree

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

4 stage, in-order, secure RISC-V core based on the CV32E40P

4 stage, in-order, compute RISC-V core based on the CV32E40P

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)

Functional verification project for the CORE-V family of RISC-V cores.