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The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

Instruction Set Generator initially contributed by Futurewei

Unofficial development fork of U-Boot

4 stage, in-order, secure RISC-V core based on the CV32E40P

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

Eclipse/FreeRTOS/core-v-mcu example program

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

CVA6 SDK containing RISC-V tools and Buildroot

Main Repo for the OpenHW Group Software Task Group

The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.

This is a private repo with tools and 'how-to' documentation for OpenHW Staff to use. We may make this repo public at some point.

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Functional verification project for the CORE-V family of RISC-V cores.