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Aidge's core module, written in C++, always required

Read-only wrapper library for OSI (ASAM Open Simulation Interface) to provide easy access to data even in aggregated form

A standalone simulator which can be used to run an OpenScenario based simulation.

Aidge's core module, written in C++, always required

Papyrus for Designer

Papyrus for Robotics

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

Instruction Set Generator initially contributed by Futurewei

Eclipse/FreeRTOS/core-v-mcu example program

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

Aidge's OpenCV backend, written in C++, for image data loading and some CV operators implementation

Julian Skublics etrice fork