4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
Functional verification project for the CORE-V family of RISC-V cores.
CV32E40S Design-Verification environment
Oniro Project Security updates
Unofficial development fork of U-Boot
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
Linux kernel source tree
3rd party: Fork of https://git.yoctoproject.org/linux-yocto