Explore projects

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

CVA6 SDK containing RISC-V tools and Buildroot

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

Aidge bundle repository, which includes the main modules of the Aidge framework, plus the documentation and tutorials.

Aidge meta-repository, which includes the main modules of the Aidge framework as Git submodules, plus the documentation and tutorials.

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Read-only wrapper library for OSI (ASAM Open Simulation Interface) to provide easy access to data even in aggregated form

Example SDK applications for DevKit

CV32E40X Design-Verification environment

The OpenPiton Platform

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

Unofficial development fork of U-Boot