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The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Instruction Set Generator initially contributed by Futurewei

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Aidge bundle repository, which includes the main modules of the Aidge framework, plus the documentation and tutorials.

Tutorials and container specification