Explore projects

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Instruction Set Generator initially contributed by Futurewei

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Aidge bundle repository, which includes the main modules of the Aidge framework, plus the documentation and tutorials.

Tutorials and container specification

Slight edit to adapt ease for Python 3.12 & more