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Linux kernel source tree

Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)

Eclipse/FreeRTOS/core-v-mcu example program

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

CORE-ET Silicon Platform

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.

Yocto layer for CVA6

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

4 stage, in-order, compute RISC-V core based on the CV32E40P

CVA6 SDK containing RISC-V tools and Buildroot

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

OpenHW Group is a global, not-for-profit organization where hardware and software designers collaborate on open-source cores, IP, tools, and software. It provides infrastructure to host high-quality open-source hardware projects aligned with industry best practices.

Graphene installation and maintenance scripts

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