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CORE-V MCU UVM Environment and Test Bench

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

downloads.openhwgroup.org

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Linux kernel source tree

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

Unofficial development fork of U-Boot

Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)

Eclipse/FreeRTOS/core-v-mcu example program

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

4 stage, in-order, secure RISC-V core based on the CV32E40P

Small and simple APB interrupt controller