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4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

The subproject opSimulation mainly consists of the simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/technology.simopenpass

The subproject opSimulation mainly consists of the simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/automotive.openpass

eTrice

Titan Project

Functional verification project for the CORE-V family of RISC-V cores.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

CV32E40X Design-Verification environment

CVA6 SDK containing RISC-V tools and Buildroot