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The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

Functional verification project for the CORE-V family of RISC-V cores.

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform

Unified Access Page for the TRISTAN project

4 stage, in-order, compute RISC-V core based on the CV32E40P

CV32E40X Design-Verification environment

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Main Repo for the OpenHW Group Software Task Group

OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

CV32E40X Design-Verification environment