Explore projects

Aidge bundle repository, which includes the main modules of the Aidge framework, plus the documentation and tutorials.

Eclipse ESCET project main repository.

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

eTrice

UVM Verification Environment for the CVFPU

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

CVA6 SDK containing RISC-V tools and Buildroot

Functional verification project for the CORE-V family of RISC-V cores.

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

UVM Verification Environment for the CVFPU

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Functional verification project for the CORE-V family of RISC-V cores.

CVA6 SDK containing RISC-V tools and Buildroot