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Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Aidge's quantization module, for both PTQ and QAT, written in C++

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Functional verification project for the CORE-V family of RISC-V cores.

Aidge's reference CPU backend, written in C++, not optimized for performances

Aidge's ONNX import/export module, written in Python, required for ONNX interoperability

The subproject opSimulation mainly consists of the simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/technology.simopenpass

Oniro Project Documentation

The HDAG and source of the customer dashboard.

Aidge's core module, written in C++, always required

Aidge's core module, written in C++, always required