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EDDIE: enable intelligence in Oniro

This repository contains the sources for the Eclipse Project Handbook. All content is represented in Asciidoc format and Asciidoctor is used to render the content into HTML, PDF, and EPUB formats. Note that the documents are all rendered complete (i.e. images and other resources are embedded).

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.

Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board

Instruction Set Generator initially contributed by Futurewei

OpenEmbedded layer for building OpenHarmony images and components.

3rd party: fork of https://gitlab.com/Linaro/trustedsubstrate/meta-ledge-secure

3rd party: Fork of https://git.yoctoproject.org/linux-yocto

CVA6 SDK containing RISC-V tools and Buildroot

Aidge's CUDA backend, written in C++/CUDA and using NVidia's CuDNN and CuBLAS libraries. Required for training and inference on NVidia's GPUs

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

Aidge's CUDA backend, written in C++/CUDA and using NVidia's CuDNN and CuBLAS libraries. Required for training and inference on NVidia's GPUs

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