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    9cf03cbd
    ARM: 7635/1: versatile: fix the PCI IRQ regression · 9cf03cbd
    Bruce Ashfield authored
    
    1/2 [
    Author: Linus Walleij
    Email: linus.walleij@linaro.org
    Subject: ARM: 7635/1: versatile: fix the PCI IRQ regression
    Date: Mon, 28 Jan 2013 21:58:22 +0100
    
    upstream commit: e3e92a7be6936dff1de80e66b0b683d54e9e02d8
    
    The PCI IRQs were regressing due to two things:
    
    - The PCI glue layer was using an hard-coded IRQ 27 offset.
      This caused the immediate regression.
    
    - The SIC IRQ mask was inverted (i.e. a bit was indeed set to
      one for each valid IRQ on the SIC, but accidentally inverted
      in the init call). This has been around forever, but we have
      been saved by some other forgiving code that would reserve
      IRQ descriptors in this range, as the versatile is
      non-sparse.
    
    When the IRQs were bumped up 32 steps so as to avoid using IRQ
    zero and avoid touching the 16 legacy IRQs, things broke.
    
    Introduce an explicit valid mask for the IRQs that are active
    on the PIC/SIC, and pass that. Use the BIT() macro from
    <linux/bitops.h> to make sure we hit the right bits, readily
    defined in <mach/platform.h>.
    
    Reported-by: default avatarTetsuo Handa <penguin-kernel@i-love.sakura.ne.jp>
    Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    Signed-off-by: default avatarBruce Ashfield <bruce.ashfield@windriver.com>
    ]
    
    2/2 [
    Author: Paul Gortmaker
    Email: paul.gortmaker@windriver.com
    Subject: arm: add dummy swizzle for versatile with qemu
    Date: Tue, 26 Feb 2013 15:35:22 -0500
    
    Booting the ARM versatile in qemu fails with the SCSI controller
    timing out as follows:
    
     ------------
     sym0: <895a> rev 0x0 at pci 0000:00:0d.0 irq 92
     sym0: SCSI BUS has been reset.
     scsi0 : sym-2.2.3
     [...]
     scsi 0:0:0:0: ABORT operation started
     scsi 0:0:0:0: ABORT operation timed-out.
     scsi 0:0:0:0: DEVICE RESET operation started
     scsi 0:0:0:0: DEVICE RESET operation timed-out.
     scsi 0:0:0:0: BUS RESET operation started
     scsi 0:0:0:0: BUS RESET operation timed-out.
     scsi 0:0:0:0: HOST RESET operation started
     sym0: SCSI BUS has been reset
     ------------
    
    Bisecting gives commit 1bc39ac5dab265b76ce6e20d6c85f900539fd190
    ("ARM: PCI: versatile: fix PCI interrupt setup") -- specifically
    the change to use common swizzle instead of NULL.  However, a
    revert of that isn't sufficient, since another change in commit
    daeb4c0c3bf2df72d0cd6e4330bad9e2e520552b ("ARM: PCI: get rid of
    pci_std_swizzle()") makes a NULL swizzle implicitly mean to use
    the common one.  So to effectively "revert" the behaviour of
    commit 1bc39ac5d, we have to introduce a no-op swizzle for the
    versatile platform.
    
    It is unclear what the "real" hardware swizzle is for this
    platform, if it actually has one.  If it doesn't, then it
    really can't support PCI cards with their own bridge onboard.
    
    Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
    Signed-off-by: default avatarBruce Ashfield <bruce.ashfield@windriver.com>
    ]
    
    Signed-off-by: default avatarBruce Ashfield <bruce.ashfield@windriver.com>
    9cf03cbd
    History
    ARM: 7635/1: versatile: fix the PCI IRQ regression
    Bruce Ashfield authored
    
    1/2 [
    Author: Linus Walleij
    Email: linus.walleij@linaro.org
    Subject: ARM: 7635/1: versatile: fix the PCI IRQ regression
    Date: Mon, 28 Jan 2013 21:58:22 +0100
    
    upstream commit: e3e92a7be6936dff1de80e66b0b683d54e9e02d8
    
    The PCI IRQs were regressing due to two things:
    
    - The PCI glue layer was using an hard-coded IRQ 27 offset.
      This caused the immediate regression.
    
    - The SIC IRQ mask was inverted (i.e. a bit was indeed set to
      one for each valid IRQ on the SIC, but accidentally inverted
      in the init call). This has been around forever, but we have
      been saved by some other forgiving code that would reserve
      IRQ descriptors in this range, as the versatile is
      non-sparse.
    
    When the IRQs were bumped up 32 steps so as to avoid using IRQ
    zero and avoid touching the 16 legacy IRQs, things broke.
    
    Introduce an explicit valid mask for the IRQs that are active
    on the PIC/SIC, and pass that. Use the BIT() macro from
    <linux/bitops.h> to make sure we hit the right bits, readily
    defined in <mach/platform.h>.
    
    Reported-by: default avatarTetsuo Handa <penguin-kernel@i-love.sakura.ne.jp>
    Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
    Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    Signed-off-by: default avatarBruce Ashfield <bruce.ashfield@windriver.com>
    ]
    
    2/2 [
    Author: Paul Gortmaker
    Email: paul.gortmaker@windriver.com
    Subject: arm: add dummy swizzle for versatile with qemu
    Date: Tue, 26 Feb 2013 15:35:22 -0500
    
    Booting the ARM versatile in qemu fails with the SCSI controller
    timing out as follows:
    
     ------------
     sym0: <895a> rev 0x0 at pci 0000:00:0d.0 irq 92
     sym0: SCSI BUS has been reset.
     scsi0 : sym-2.2.3
     [...]
     scsi 0:0:0:0: ABORT operation started
     scsi 0:0:0:0: ABORT operation timed-out.
     scsi 0:0:0:0: DEVICE RESET operation started
     scsi 0:0:0:0: DEVICE RESET operation timed-out.
     scsi 0:0:0:0: BUS RESET operation started
     scsi 0:0:0:0: BUS RESET operation timed-out.
     scsi 0:0:0:0: HOST RESET operation started
     sym0: SCSI BUS has been reset
     ------------
    
    Bisecting gives commit 1bc39ac5dab265b76ce6e20d6c85f900539fd190
    ("ARM: PCI: versatile: fix PCI interrupt setup") -- specifically
    the change to use common swizzle instead of NULL.  However, a
    revert of that isn't sufficient, since another change in commit
    daeb4c0c3bf2df72d0cd6e4330bad9e2e520552b ("ARM: PCI: get rid of
    pci_std_swizzle()") makes a NULL swizzle implicitly mean to use
    the common one.  So to effectively "revert" the behaviour of
    commit 1bc39ac5d, we have to introduce a no-op swizzle for the
    versatile platform.
    
    It is unclear what the "real" hardware swizzle is for this
    platform, if it actually has one.  If it doesn't, then it
    really can't support PCI cards with their own bridge onboard.
    
    Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
    Signed-off-by: default avatarBruce Ashfield <bruce.ashfield@windriver.com>
    ]
    
    Signed-off-by: default avatarBruce Ashfield <bruce.ashfield@windriver.com>
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