ARM: 7635/1: versatile: fix the PCI IRQ regression

1/2 [
Author: Linus Walleij
Email: linus.walleij@linaro.org
Subject: ARM: 7635/1: versatile: fix the PCI IRQ regression
Date: Mon, 28 Jan 2013 21:58:22 +0100

upstream commit: e3e92a7be6936dff1de80e66b0b683d54e9e02d8

The PCI IRQs were regressing due to two things:

- The PCI glue layer was using an hard-coded IRQ 27 offset.
  This caused the immediate regression.

- The SIC IRQ mask was inverted (i.e. a bit was indeed set to
  one for each valid IRQ on the SIC, but accidentally inverted
  in the init call). This has been around forever, but we have
  been saved by some other forgiving code that would reserve
  IRQ descriptors in this range, as the versatile is
  non-sparse.

When the IRQs were bumped up 32 steps so as to avoid using IRQ
zero and avoid touching the 16 legacy IRQs, things broke.

Introduce an explicit valid mask for the IRQs that are active
on the PIC/SIC, and pass that. Use the BIT() macro from
<linux/bitops.h> to make sure we hit the right bits, readily
defined in <mach/platform.h>.

Reported-by: Tetsuo Handa <penguin-kernel@i-love.sakura.ne.jp>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]

2/2 [
Author: Paul Gortmaker
Email: paul.gortmaker@windriver.com
Subject: arm: add dummy swizzle for versatile with qemu
Date: Tue, 26 Feb 2013 15:35:22 -0500

Booting the ARM versatile in qemu fails with the SCSI controller
timing out as follows:

 ------------
 sym0: <895a> rev 0x0 at pci 0000:00:0d.0 irq 92
 sym0: SCSI BUS has been reset.
 scsi0 : sym-2.2.3
 [...]
 scsi 0:0:0:0: ABORT operation started
 scsi 0:0:0:0: ABORT operation timed-out.
 scsi 0:0:0:0: DEVICE RESET operation started
 scsi 0:0:0:0: DEVICE RESET operation timed-out.
 scsi 0:0:0:0: BUS RESET operation started
 scsi 0:0:0:0: BUS RESET operation timed-out.
 scsi 0:0:0:0: HOST RESET operation started
 sym0: SCSI BUS has been reset
 ------------

Bisecting gives commit 1bc39ac5dab265b76ce6e20d6c85f900539fd190
("ARM: PCI: versatile: fix PCI interrupt setup") -- specifically
the change to use common swizzle instead of NULL.  However, a
revert of that isn't sufficient, since another change in commit
daeb4c0c3bf2df72d0cd6e4330bad9e2e520552b ("ARM: PCI: get rid of
pci_std_swizzle()") makes a NULL swizzle implicitly mean to use
the common one.  So to effectively "revert" the behaviour of
commit 1bc39ac5d, we have to introduce a no-op swizzle for the
versatile platform.

It is unclear what the "real" hardware swizzle is for this
platform, if it actually has one.  If it doesn't, then it
really can't support PCI cards with their own bridge onboard.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]

Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>

bsp/arm-versatile-926ejs/ARM-7635-1-versatile-fix-the-PCI-IRQ-regression.patch

+From b81895996f54cdbfd965acf3de5a951395c60627 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 28 Jan 2013 21:58:22 +0100
+Subject: [PATCH 1/2] ARM: 7635/1: versatile: fix the PCI IRQ regression
+
+upstream commit: e3e92a7be6936dff1de80e66b0b683d54e9e02d8
+
+The PCI IRQs were regressing due to two things:
+
+- The PCI glue layer was using an hard-coded IRQ 27 offset.
+  This caused the immediate regression.
+
+- The SIC IRQ mask was inverted (i.e. a bit was indeed set to
+  one for each valid IRQ on the SIC, but accidentally inverted
+  in the init call). This has been around forever, but we have
+  been saved by some other forgiving code that would reserve
+  IRQ descriptors in this range, as the versatile is
+  non-sparse.
+
+When the IRQs were bumped up 32 steps so as to avoid using IRQ
+zero and avoid touching the 16 legacy IRQs, things broke.
+
+Introduce an explicit valid mask for the IRQs that are active
+on the PIC/SIC, and pass that. Use the BIT() macro from
+<linux/bitops.h> to make sure we hit the right bits, readily
+defined in <mach/platform.h>.
+
+Reported-by: Tetsuo Handa <penguin-kernel@i-love.sakura.ne.jp>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
+---
+ arch/arm/mach-versatile/core.c |   15 ++++++++++++++-
+ arch/arm/mach-versatile/pci.c  |   11 ++++++-----
+ 2 files changed, 20 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
+index 5dce252..fcb6784 100644
+--- a/arch/arm/mach-versatile/core.c
++++ b/arch/arm/mach-versatile/core.c
+@@ -38,6 +38,7 @@
+ #include <linux/gfp.h>
+ #include <linux/clkdev.h>
+ #include <linux/mtd/physmap.h>
++#include <linux/bitops.h>
+ 
+ #include <asm/irq.h>
+ #include <asm/hardware/arm_timer.h>
+@@ -67,16 +68,28 @@
+ #define VA_VIC_BASE		__io_address(VERSATILE_VIC_BASE)
+ #define VA_SIC_BASE		__io_address(VERSATILE_SIC_BASE)
+ 
++/* These PIC IRQs are valid in each configuration */
++#define PIC_VALID_ALL	BIT(SIC_INT_KMI0) | BIT(SIC_INT_KMI1) | \
++			BIT(SIC_INT_SCI3) | BIT(SIC_INT_UART3) | \
++			BIT(SIC_INT_CLCD) | BIT(SIC_INT_TOUCH) | \
++			BIT(SIC_INT_KEYPAD) | BIT(SIC_INT_DoC) | \
++			BIT(SIC_INT_USB) | BIT(SIC_INT_PCI0) | \
++			BIT(SIC_INT_PCI1) | BIT(SIC_INT_PCI2) | \
++			BIT(SIC_INT_PCI3)
+ #if 1
+ #define IRQ_MMCI0A	IRQ_VICSOURCE22
+ #define IRQ_AACI	IRQ_VICSOURCE24
+ #define IRQ_ETH		IRQ_VICSOURCE25
+ #define PIC_MASK	0xFFD00000
++#define PIC_VALID	PIC_VALID_ALL
+ #else
+ #define IRQ_MMCI0A	IRQ_SIC_MMCI0A
+ #define IRQ_AACI	IRQ_SIC_AACI
+ #define IRQ_ETH		IRQ_SIC_ETH
+ #define PIC_MASK	0
++#define PIC_VALID	PIC_VALID_ALL | BIT(SIC_INT_MMCI0A) | \
++			BIT(SIC_INT_MMCI1A) | BIT(SIC_INT_AACI) | \
++			BIT(SIC_INT_ETH)
+ #endif
+ 
+ /* Lookup table for finding a DT node that represents the vic instance */
+@@ -104,7 +117,7 @@ void __init versatile_init_irq(void)
+ 					      VERSATILE_SIC_BASE);
+ 
+ 	fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
+-		IRQ_VICSOURCE31, ~PIC_MASK, np);
++		IRQ_VICSOURCE31, PIC_VALID, np);
+ 
+ 	/*
+ 	 * Interrupts on secondary controller from 0 to 8 are routed to
+diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
+index 2f84f40..e92e5e0 100644
+--- a/arch/arm/mach-versatile/pci.c
++++ b/arch/arm/mach-versatile/pci.c
+@@ -23,6 +23,7 @@
+ #include <linux/io.h>
+ 
+ #include <mach/hardware.h>
++#include <mach/irqs.h>
+ #include <asm/irq.h>
+ #include <asm/mach/pci.h>
+ 
+@@ -327,12 +328,12 @@ static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+ 	int irq;
+ 
+ 	/* slot,  pin,	irq
+-	 *  24     1     27
+-	 *  25     1     28
+-	 *  26     1     29
+-	 *  27     1     30
++	 *  24     1     IRQ_SIC_PCI0
++	 *  25     1     IRQ_SIC_PCI1
++	 *  26     1     IRQ_SIC_PCI2
++	 *  27     1     IRQ_SIC_PCI3
+ 	 */
+-	irq = 27 + ((slot - 24 + pin - 1) & 3);
++	irq = IRQ_SIC_PCI0 + ((slot - 24 + pin - 1) & 3);
+ 
+ 	return irq;
+ }
+-- 
+1.7.10.4
+

bsp/arm-versatile-926ejs/arm-add-dummy-swizzle-for-versatile-with-qemu.patch

+From 351d133943b50a9dfeee07661d44254722a19f04 Mon Sep 17 00:00:00 2001
+From: Paul Gortmaker <paul.gortmaker@windriver.com>
+Date: Tue, 26 Feb 2013 15:35:22 -0500
+Subject: [PATCH 2/2] arm: add dummy swizzle for versatile with qemu
+
+Booting the ARM versatile in qemu fails with the SCSI controller
+timing out as follows:
+
+ ------------
+ sym0: <895a> rev 0x0 at pci 0000:00:0d.0 irq 92
+ sym0: SCSI BUS has been reset.
+ scsi0 : sym-2.2.3
+ [...]
+ scsi 0:0:0:0: ABORT operation started
+ scsi 0:0:0:0: ABORT operation timed-out.
+ scsi 0:0:0:0: DEVICE RESET operation started
+ scsi 0:0:0:0: DEVICE RESET operation timed-out.
+ scsi 0:0:0:0: BUS RESET operation started
+ scsi 0:0:0:0: BUS RESET operation timed-out.
+ scsi 0:0:0:0: HOST RESET operation started
+ sym0: SCSI BUS has been reset
+ ------------
+
+Bisecting gives commit 1bc39ac5dab265b76ce6e20d6c85f900539fd190
+("ARM: PCI: versatile: fix PCI interrupt setup") -- specifically
+the change to use common swizzle instead of NULL.  However, a
+revert of that isn't sufficient, since another change in commit
+daeb4c0c3bf2df72d0cd6e4330bad9e2e520552b ("ARM: PCI: get rid of
+pci_std_swizzle()") makes a NULL swizzle implicitly mean to use
+the common one.  So to effectively "revert" the behaviour of
+commit 1bc39ac5d, we have to introduce a no-op swizzle for the
+versatile platform.
+
+It is unclear what the "real" hardware swizzle is for this
+platform, if it actually has one.  If it doesn't, then it
+really can't support PCI cards with their own bridge onboard.
+
+Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
+---
+ arch/arm/mach-versatile/pci.c |    6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
+index e92e5e0..03b679c 100644
+--- a/arch/arm/mach-versatile/pci.c
++++ b/arch/arm/mach-versatile/pci.c
+@@ -338,7 +338,13 @@ static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+ 	return irq;
+ }
+ 
++static u8 versatile_swizzle(struct pci_dev *dev, u8 *pinp)
++{
++	return 0;
++}
++
+ static struct hw_pci versatile_pci __initdata = {
++	.swizzle		= versatile_swizzle,
+ 	.map_irq		= versatile_map_irq,
+ 	.nr_controllers		= 1,
+ 	.ops			= &pci_versatile_ops,
+-- 
+1.7.10.4
+

bsp/arm-versatile-926ejs/arm-versatile-926ejs.scc

@@ -6,3 +6,5 @@ include features/latencytop/latencytop.scc
 
 patch arm_versatile_926ejs-add-default-nor-flash-mtd-parts.patch
 patch arm_versatile_926ejs-kick-off-PrimeCell-RTC-PL031.patch
+patch ARM-7635-1-versatile-fix-the-PCI-IRQ-regression.patch
+patch arm-add-dummy-swizzle-for-versatile-with-qemu.patch