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rgiunti authored
Multi-Tool Support (Questasim, Xcelium, VCS) and Unified Compilation Flow for cvfpu-uvm with Bender support (#2) * status_env.sh, Makefile modified for supporting xcelium and vcs * adding yaml files for xcelium * modified import order in fpu_refmodel_pkg.sv for fixing xrun -compile * adding -timescale option for elaboration in sim_xcelium.yaml * .gitignore updated for discarding .history files * adding support for xcelium simulation * gitmodules updated * .gitmodules restored for repo * Working support Xcelium (comp to reg list simulation) * removing reg yaml files: the sim yaml files are identical * adding single filelist * top yaml files modified for using single filelist and debug capabilities * setup files modified for supporting VCS * modified regression list with just random tests * changing sim_pattern for recognizing VCS EOT * removing unuseful yaml files and unused xcelium tcl files * unpacked arrays in transaction file for VCS compatibility * removing all remaining yaml files, unused because of the single file * better setting of comp options in yaml files * updated README with latest modifications * README fixed * README fixed pt2 * README: added note on git submodules * commenting setup_env for not updating openhw submodules * changing filelist for Bender in sim_questa.yaml * updating top yaml files with bender filelist name * adding Bender.yml * removing comp_filelist.f: not used anymore * updating gitignore * modify urls to chips-it branch in setup.sh and Bender.yml * updated fpu_reg_list for performing long test * updated gitmodules with ChipsIT links and updated readme * Update README.md Co-authored-by:
Yvan Tortorella <48508508+yvantor@users.noreply.github.com> * Update README.md Co-authored-by:
rgiunti <riccardo.giunti@chips.it> Co-authored-by:
rgiunti authoredMulti-Tool Support (Questasim, Xcelium, VCS) and Unified Compilation Flow for cvfpu-uvm with Bender support (#2) * status_env.sh, Makefile modified for supporting xcelium and vcs * adding yaml files for xcelium * modified import order in fpu_refmodel_pkg.sv for fixing xrun -compile * adding -timescale option for elaboration in sim_xcelium.yaml * .gitignore updated for discarding .history files * adding support for xcelium simulation * gitmodules updated * .gitmodules restored for repo * Working support Xcelium (comp to reg list simulation) * removing reg yaml files: the sim yaml files are identical * adding single filelist * top yaml files modified for using single filelist and debug capabilities * setup files modified for supporting VCS * modified regression list with just random tests * changing sim_pattern for recognizing VCS EOT * removing unuseful yaml files and unused xcelium tcl files * unpacked arrays in transaction file for VCS compatibility * removing all remaining yaml files, unused because of the single file * better setting of comp options in yaml files * updated README with latest modifications * README fixed * README fixed pt2 * README: added note on git submodules * commenting setup_env for not updating openhw submodules * changing filelist for Bender in sim_questa.yaml * updating top yaml files with bender filelist name * adding Bender.yml * removing comp_filelist.f: not used anymore * updating gitignore * modify urls to chips-it branch in setup.sh and Bender.yml * updated fpu_reg_list for performing long test * updated gitmodules with ChipsIT links and updated readme * Update README.md Co-authored-by:
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