feat: Add support for SVNAPOT extension

Description

The CVA6 processor core lacked support for the RISC-V Svnapot (Naturally Aligned Power-of-Two) extension. The primary motivation for this feature is to improve MMU performance by allowing a single TLB entry to map a large, contiguous 64KiB memory region, thereby reducing TLB misses for memory-intensive applications. With this implementation Svnapot will be supported in CVA6 core.

Changes

1. Page Table Walker (cva6_ptw.sv):

• The PTW now correctly detects a 64KiB NAPOT PTE (N=1, PPN[3:0] = 4'b1000).

• Upon detection, it forwards the unmodified PTE to the TLB update interface.

• A new signal, napot_bits, is propagated alongside the PTE to flag it as a NAPOT entry for the TLB.

2. TLBs (cva6_tlb.sv and cva6_shared_tlb.sv):

• The TLB storage (tags_q, content_q) has been extended to include the napot_bits field, allowing each entry to be identified as a standard or NAPOT page.

• Tag Comparison Logic: The lookup logic has been significantly updated. When comparing tags for an entry where napot_bits is set, the lower 4 bits of the Virtual Page Number (VPN) are masked (ignored). This ensures that any virtual address within the 64KiB range correctly matches the single NAPOT TLB entry.

• On-Hit PPN Patching: This is the core of the fix. Upon a successful tag match with a NAPOT entry, the final PPN is constructed by taking the stored PPN template and overwriting its lower 4 bits (PPN[3:0]) with the corresponding bits from the incoming virtual address (vaddr[15:12]).

3. Memory Management Unit (cva6_mmu.sv):

• The MMU has been updated to correctly handle the patched PPN and napot_bits coming from the ITLB and DTLB on a hit, ensuring the final physical address is calculated correctly.

How to Test

• Compile the CVA6 core with the changes from this pull request.

• You may use the napot.S test from the official RISCV repository https://github.com/riscv-software-src/riscv-tests/tree/master/isa/rv64ssvnapot.

• Run the napot directed tests.

• The napot.S test should PASS without any timeout or failure.

CC @Jbalkind, @niwis