Fix incorrect interrupt cause encoding in RV64 (Issue #3093)

Summary

Fixes incorrect interrupt cause encoding in RV64 mode by using explicit bit-width casting for literals in the INTERRUPTS localparam.

Problem

• Literal 1 in (1 << (CVA6Cfg.XLEN - 1)) is treated as 32-bit by Synopsys VCS
• In RV64 mode, (32'b1 << 63) causes overflow, resulting in incorrect interrupt cause encoding
• All interrupts cannot be properly identified in RV64 mode

Solution

• Replace (1 << (CVA6Cfg.XLEN - 1)) with (CVA6Cfg.XLEN'(1) << (CVA6Cfg.XLEN - 1))
• Explicit bit-width casting ensures correct literal size for both RV32 and RV64
• Prevents overflow in left shift operation

Changes

• File: core/cva6.sv
• Lines: Updated INTERRUPTS localparam (lines 355-364)
• Impact: Fixes all 10 interrupt types (S_SW, VS_SW, M_SW, S_TIMER, VS_TIMER, M_TIMER, S_EXT, VS_EXT, M_EXT, HS_EXT)

Technical Details

• RV32: No change in behavior (was working correctly)
• RV64: Interrupt cause encoding now works correctly
• Bit-width: CVA6Cfg.XLEN'(1) creates literal with correct width (32 or 64 bits)
• MSB Setting: Ensures MSB is properly set for interrupt identification

Testing

• ✅ Syntax check passed
• ✅ Logic analysis verified
• ✅ No linting errors
• ✅ All 10 interrupt types updated consistently

Fixes #3093 (closed)