Add `early_valid` signal to check for structural hazards

In CVA6, the FPU shares a writeback port with the secondary ALU used in superscalar mode. Until now, FPU support was disabled to prevent structural hazards. To enable FPU support in superscalar mode, an additional signal is required to indicate when the FPU will produce a valid result in the next cycle. This occurs in two cases:

• A valid result is currently in the penultimate pipeline stage.
• A valid result is in the final pipeline stage, but the ready signal was not asserted in the current cycle.